1. Technical Field
This invention generally relates to systems for measuring clock error, and more specifically relates to a built-in self measurement circuit for measuring output clock error of Phase Lock Loop Circuits.
2. Background Art
A PLL (Phase Locked Loop) is widely used in logic circuits for clock generation. For instance, PLL circuits are utilized in many applications to provide an output signal that is of the same phase and frequency as an input reference signal. In addition, PLL's are widely used in Advanced Instruction Set Integrated Circuit (ASIC) chips for clock synchronization and multiplication to facilitate high speed chip to chip communication. However, like most electronic devices that manipulate clock signals, PLL's have some small amount of error associated with their operation. Because of the high degree of precision required by many of today's advanced digital systems, having knowledge of the error associated with a given PLL is important for circuit designers and manufacturers. Until now, no reliable system or method has existed to accurately measure PLL error.
As noted above, every PLL produces some amount of undesirable error (or jitter) in its output clock whose magnitude is usually small and difficult to measure. In particular, PLL output clock error may include signal delays of the output signal with respect to an input reference signal or it may involve an output signal whose frequency varies. PLL clock error plays an especially important role when dealing with high speed communication between ASIC chips, where clock latency must be removed on each ASIC chip and circuit developers must account for PLL jitter in their timing paths. Because the allowable clock skew budget between chips must be reduced by the amount of PLL jitter, accurate knowledge of PLL jitter is critical in avoiding system failures.
Unfortunately, the ability to accurately measure output clock error has become increasingly difficult because new PLL circuits have reduced PLL error to a point where production testers used for ASIC tests cannot accurately measure jitter. Furthermore, even though certain PLL parameters can be measured and tested, there exists no guarantee that a PLL could still exhibit jitter above its specification.
One known method for measuring PLL error involves the use of off chip measurement equipment. Unfortunately, these methods create problems in that the errors introduced by probes, connection cables, and the like may often be comparable to the magnitude of the error being measured. Known systems have sought to solve such problems by implementing built-in self test circuitry. U.S. Pat. No. 5,381,085 issued to Fischer entitled "Phase Lock Loop With Self Test Circuitry and Method Using the Same" discloses a system and method for measuring the ratio between the input and output frequency of a PLL. Unfortunately, this system and method fail to provide any discrete information regarding PLL output clock jitter.
Other known systems and methods have been used to calibrate clock signals, but again, none are known to provide built-in components for error measurement of a PLL. For instance, U.S. Pat. No. 5,220,581 issued to Ferraiolo et al. and assigned to International Business Machines, Inc. entitled "Digital Data Link Performance Monitor" teaches a technique for calibrating data timing jitter within a digital communication link. This system is concerned with monitoring digitally transmitted signals at a receiving point to select an appropriate clock phase. Thus, while many known systems utilize methods for performing clock recovery and clock calibration, none are known to provide a built-in system that provides an accurate and discrete measurement of clock error within a PLL circuit. Thus, a need exists for a built-in self test system for measuring PLL clock error. The aforementioned art is herein incorporated by reference.